1. Field of the Invention
Embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a core bias line stabilization circuit of a nonvolatile memory device.
2. Description of the Related Art
A semiconductor integrated circuit (IC) is provided with an internal driving voltage generation block for stably operating various internal logics and devices. In the case of a nonvolatile memory device, in particular, a NAND flash memory, biases with very various levels are needed.
A NAND flash memory performs program and read operations using a distribution of a cell threshold voltage (Vth). Although it is advantageous if the distribution of the cell threshold voltage (Vth) is narrow, as semiconductor devices shrink circuit line widths also shrink, which may cause the distribution of the cell threshold voltage (Vth) to widen.
As the distribution of the cell threshold voltage (Vth) is widened, a read operation in a negative region has been introduced. In order to read a negative region, a voltage difference between a selected word line and a source line corresponding to a source of a cell string should be negative. That is to say, the voltage of the selected word line should be lower than the source line.
There are two schemes for realizing negative read. One scheme is to apply 0V to the source line and a negative bias to the selected word line, and the other scheme is to apply 0V to the selected word line and a positive bias (VCORE) to the source line and a virtual power line. The latter is called a virtual negative read scheme.
Advantages of the virtual negative read scheme are that a negative bias is not needed and the separation of the well of the path transistor of a row decoder is not required. On the other hand, disadvantages are caused in that noise generation is substantial when applying the specified positive bias (VCORE) to the source line and the virtual power line. Such noise generation leads to a distortion of the cell threshold voltage (Vth), thereby deteriorating characteristics of a device.
FIG. 1 is a view showing cell current flow in a virtual negative read operation and the configuration of a switch circuit.
First, the configuration of the switch circuit shown in FIG. 1 will be described.
An NMOS transistor M1 receives a page buffer enable signal PBSENSE as a gate input and switches a page buffer 10 and even/odd bit lines BLe/BLo. An NMOS transistor M2 receives an even bit line sensing signal BSLe as a gate input and is connected to the even bit line BLe. An NMOS transistor M3 receives an odd bit line sensing signal BSLo as a gate input and is connected to the odd bit line BLo. An NMOS transistor M4 receives an even bit line discharge signal DISe as a gate input and switches a virtual power line VIRPWR and the even bit line BLe. An NMOS transistor M5 receives an odd bit line discharge signal DISo as a gate input and switches the virtual power line VIRPWR and the odd bit line BLo. An NMOS transistor M6 is a switch which switches a source line SL and a core voltage (VCORE) generator 12, and an NMOS transistor M7 is a switch which switches the virtual power line VIRPWR and the core voltage (VCORE) generator 12. For reference, a capacitor Ccoup connected between the even bit line BLe and the odd bit line BLo designates coupling capacitance of the even bit line BLe and the odd bit line BLo.
The figure shows a situation in which the even bit line BLe is selected in a virtual negative read operation represents a switching state of an evaluation period. In this period, the NMOS transistors M1, M4 and M3 are turned off, and the NMOS transistors M6 and M7 are turned on.
Both the even bit line BLe and the odd bit line BLo are connected to the source line SL. Cell current Ic flows through the cell string to which the even bit line BLe is connected, and current Iodd by bouncing flows through the cell string to which the odd bit line BLo is connected. As the NMOS transistors M6 and M7 are turned on, a core voltage VCORE is applied to the source line SL and the virtual power line VIRPWR. As a result, Ic-Iodd-Isw flows through the source line SL, and Ic-Iodd-Isw with an opposite direction flows through the virtual power line VIRPWR (Isw denotes switch current).
FIG. 2 is a view showing changes in the waveforms of the source line SL and the virtual power line VIRPWR while cell current Ic flows.
In order for the switch circuits such as the NMOS transistor M6 and M7 to allow current flow, a condition of Vds>0V (Vds is a drain-source voltage of an NMOS transistor) is required. In the process of setting Vds to allow current flow, noise may be generated in the source line SL and the virtual power line VIRPWR as Vds reaches a target voltage level Vtarg of the core voltage VCORE. Noise patterns are oppositely induced in the source line SL and the virtual power line VIRPWR. In other words, noise is typically generated as an overshoot in the source line SL and as an undershoot in the virtual power line VIRPWR. This may result because the cell current Ic flow in the virtual negative read operation is larger than a current driving force of the switch circuits such as the NMOS transistors M6 and M7.
As described above, the noise of the source line SL and the virtual power line VIRPWR may lead to a distortion of a cell threshold voltage (Vth), thereby deteriorating the characteristics of a device.